1. Field of the Invention
The present invention relates generally to a fabrication process for a semiconductor device. More specifically, the invention relates to a fabrication process for a MOS transistor of a salicide (self-aligned silicide) structure.
2. Description of the Related Art
Among refractory metal silicides, titanium silicide and cobalt silicide are known to have small electric resistivity and excellent heat-resistant property. Therefore, titanium silicide, for example, has been attracting attention as high heat-resistant material to be typically used in semiconductor devices. However, upon formation of a titanium silicide layer, it has been known that such titanium silicide layer tends to be highly electrically resistive by annealing at a temperature higher than or equal to 800.degree. C. after formation of the layer. Therefore, when titanium silicide is used for a semiconductor device, the condition applicable in fabrication process becomes quite severe. This drawback is common to various refractory metal silicides.
Japanese Unexamined Patent Publication (Kokai) No. Heisei 2-290018 proposes one solution for such drawbacks. Referring to FIG. 1 which shows a section of a semiconductor device, a fabrication process of the semiconductor device (hereinafter referred to as first conventional process) disclosed in the above-identified publication is as follow.
At first, in a known process, field oxide layer 2 and a gate oxide layer 3 are formed on a surface of a silicon substrate 1. Then, by reduced pressure CVD method, a polycrystalline silicon layer is deposited over the entire surface. By thermal diffusion of phosphorus, a conductive polycrystalline silicon layer 4 is formed. Subsequently, by way of sputtering, a titanium silicide layer 19 is deposited over the entire surface. Furthermore, by known lithographic technology and/or dry-etching technology, patterning is performed for the titanium silicide layer 19 and the polycrystalline silicon layer 4 to form a gate electrode wiring of a polycide structure of laminated layer of the polycrystalline silicon layer 4 and the titanium silicide 19. After forming a diffusion layer to be a source region and a drain region of a MOS transistor by ion implantation, an interlayer insulation layer 10 is deposited over the entire periphery. Then, under pyrogenic oxidation atmosphere, annealing is performed to lower the resistance of the gate electrode wiring and to activate the diffusion layer forming the source and drain regions. This annealing under the pyrogenic oxidation atmosphere, degradation of morphology of the refractory metal silicide and agglomeration of the refractory metal silicide can be suppressed.
On the other hand, Japanese Unexamined Patent Publication No. Heisei 3-46323 discloses a thermal process for overcoming the foregoing drawback. The fabrication process (hereinafter referred to as second conventional process) for the semiconductor device disclosed in the above-identified publication is as follow.
At first, the field oxide layer 2 and the gate oxide layer 3 are formed on the surface of the silicon substrate 1. After formation of the polycrystalline silicon layer forming the gate electrode wiring, an insulation layer spacer 5 is formed on the side surface of the polycrystalline silicon layer. Then, ion implantation of conductive impurity is performed to form diffusion layers 6 to be source and drain regions. Also, the polycrystalline silicon layer becomes the conductive polycrystalline silicon layer 4 by the ion implantation. After a titanium layer is deposited over the entire surface, annealing is performed under non-oxidation atmosphere to form titanium silicide layers 29a and 29b on the upper surface of the polycrystalline silicon layer 4 and the surface of the diffusion layer 6, respectively. After removing non-reacted titanium layer, annealing is again performed at a temperature range higher than or equal to 600.degree. C. and lower than or equal to 1000.degree. C., under oxygen atmosphere for a predetermined period. Thus, titanium oxide layer 14 is formed on the surfaces of the titanium silicide layers 29a and 29b. By this second annealing, agglomeration of the titanium silicide layers 29a and 29b can be suppressed.
Agglomeration of the refractory metal silicide at a high temperature has been explained by surface energy of the refractory metal silicide, grain boundary energy, and interface energy between the refractory metal silicide and silicide of the substrate and so forth. Depending upon the grain size of the refractory metal silicide and surface orientation of the silicon substrate, crystal grain becomes easily deformed to easily cause agglomeration. In terms of prevention of agglomeration, the first and second conventional processes may be effective to a certain extent. However, in the foregoing first and second conventional processes, when annealing is performed at a temperature in the order of 800 to 1000.degree. C., at which reflow of the interlayer insulation layer formed of BPSG layer occurs agglomeration can be caused. Therefore, suppression of agglomeration is limited and lowering of resistance becomes insufficient. Also, in the above-mentioned first conventional process, it is not possible to form a MOS transistor in a salicide structure. On the other hand, in the above-mentioned second conventional process, because of subjecting to second annealing, the process becomes not applicable in the case where the depth of binding of the diffusion layer becomes small due to reduction of the size of the semiconductor device.